qilisdk.digital.circuit_transpiler

Classes

TranspilerPassResult	Per-pass transpilation artifact containing pass identity and output circuit.
CircuitTranspilerResult	Result of a full transpiler run with pass-by-pass diagnostics.
CircuitTranspiler	Orchestrate an ordered sequence of circuit transpilation passes.

Module Contents

class TranspilerPassResult(name: str, circuit: qilisdk.digital.Circuit)

Per-pass transpilation artifact containing pass identity and output circuit.

property name: str

Pass class name.

property circuit: qilisdk.digital.Circuit

Circuit produced right after this pass.

class CircuitTranspilerResult(circuit: qilisdk.digital.Circuit, intermediate_results: list[TranspilerPassResult] | None = None, layout: qilisdk.digital.types.LayoutMap | None = None, metrics: dict[str, Any] | None = None)

Result of a full transpiler run with pass-by-pass diagnostics.

property circuit: qilisdk.digital.Circuit

Alias for the final transpiled circuit.

property intermediate_results: list[TranspilerPassResult]

Ordered per-pass outputs.

property layout: qilisdk.digital.types.LayoutMap | None

Final user-facing logical-to-physical mapping captured after the pipeline finishes.

property metrics: dict[str, Any]

Metrics collected by transpiler passes.

class CircuitTranspiler(pipeline: list[qilisdk.digital.circuit_transpiler_passes.CircuitTranspilerPass])

Orchestrate an ordered sequence of circuit transpilation passes.

Instantiate this class directly when you need full control over the pass pipeline. For common workflows, use default() to build a standard pipeline for basis conversion only or for topology-aware transpilation.

Each pass receives the circuit produced by the previous pass and must return a new circuit, which makes the overall transpilation flow deterministic and easy to inspect through transpile().

Parámetros:

pipeline (list[CircuitTranspilerPass]) – Ordered passes to run during transpilation.

classmethod default(single_qubit_basis: qilisdk.digital.circuit_transpiler_passes.SingleQubitGateBasis = SingleQubitGateBasis.U3, two_qubit_basis: qilisdk.digital.circuit_transpiler_passes.TwoQubitGateBasis = TwoQubitGateBasis.CNOT, topology: qilisdk.digital.types.Topology | None = None, qubit_mapping: qilisdk.digital.types.LayoutMap | None = None) → Self

Build the default transpiler pipeline.

Use this constructor for the standard transpilation flow. When topology is omitted, the returned transpiler only performs generic decomposition and simplification passes. When topology is provided, the pipeline becomes hardware aware: it either computes a placement with SABRE and routes the circuit automatically, or it enforces a user-provided logical-to-physical layout through qubit_mapping.

Parámetros:

• single_qubit_basis (SingleQubitGateBasis) – Target single-qubit basis used by canonical decomposition and final single-qubit fusion.

• two_qubit_basis (TwoQubitGateBasis) – Target two-qubit entangling gate used by canonical decomposition.

• topology (Topology | None) – Optional hardware coupling map. It can be provided either as a list of connected physical-qubit pairs or as a rustworkx PyGraph whose node indices are physical qubits.

• qubit_mapping (LayoutMap | None) – Optional logical-to-physical qubit assignment. This argument is only used when topology is provided. If omitted, the pipeline uses SabreLayoutPass and SabreSwapPass. If provided, the pipeline uses CustomLayoutPass to preserve the requested mapping.

Devuelve:

A CircuitTranspiler instance configured with the default pass sequence for the requested transpilation mode.

Tipo del valor devuelto:

CircuitTranspiler

transpile(circuit: qilisdk.digital.Circuit) → CircuitTranspilerResult

Run the pipeline and return pass-by-pass transpilation diagnostics.

Parámetros:

circuit (Circuit) – Input circuit to transpile.

Devuelve:

Final circuit and intermediate pass outputs.

Tipo del valor devuelto:

CircuitTranspilerRunResult